/**
 * @copyright 2018 indie Semiconductor
 *
 * This file is proprietary to indie Semiconductor.
 * All rights reserved. Reproduction or distribution, in whole
 * or in part, is forbidden except by express written permission
 * of indie Semiconductor.
 *
 * @file gpioa_sfr.h
 */

#ifndef __GPIOA_SFR_H__
#define __GPIOA_SFR_H__

#include <stdint.h>

/* -------  Start of section using anonymous unions and disabling warnings  ------- */
#if   defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif

/**
 * @brief A structure to represent Special Function Registers for GPIOA.
 */

typedef struct{
    uint8_t  DIR                     :  1; /*!< Pin 0 output enable */
    uint8_t  IE                      :  1; /*!< Pin 0 interrupt mask */
    uint8_t  RE                      :  1; /*!< Pin 0 rising edge enable */
    uint8_t  FE                      :  1; /*!< Pin 0 falling edge enable */
    uint8_t  CLR                     :  1; /*!< Pin 0 interrupt clear */
    uint8_t  ACTDET                  :  1; /*!< Pin 0 activity interrupt */
    uint8_t                           :  2; /*   (reserved) */
}Port_t;

typedef struct {

  uint8_t  GPADATA[1024];                     /*<! Port A data +0x000 */

  uint8_t  GPAENA;                            /* +0x400 */
  uint8_t  _RESERVED_401[3];                  /* +0x401 */

  union {
//    struct {
//      uint8_t  DIR0                     :  1; /*!< Pin 0 output enable */
//      uint8_t  IE0                      :  1; /*!< Pin 0 interrupt mask */
//      uint8_t  RE0                      :  1; /*!< Pin 0 rising edge enable */
//      uint8_t  FE0                      :  1; /*!< Pin 0 falling edge enable */
//      uint8_t  CLR0                     :  1; /*!< Pin 0 interrupt clear */
//      uint8_t  ACTDET0                  :  1; /*!< Pin 0 activity interrupt */
//      uint8_t                           :  2; /*   (reserved) */
//      uint8_t  DIR1                     :  1; /*!< Pin 1 output enable */
//      uint8_t  IE1                      :  1; /*!< Pin 1 interrupt mask */
//      uint8_t  RE1                      :  1; /*!< Pin 1 rising edge enable */
//      uint8_t  FE1                      :  1; /*!< Pin 1 falling edge enable */
//      uint8_t  CLR1                     :  1; /*!< Pin 1 interrupt clear */
//      uint8_t  ACTDET1                  :  1; /*!< Pin 1 activity interrupt */
//      uint8_t                           :  2; /*   (reserved) */
//      uint8_t  DIR2                     :  1; /*!< Pin 2 output enable */
//      uint8_t  IE2                      :  1; /*!< Pin 2 interrupt mask */
//      uint8_t  RE2                      :  1; /*!< Pin 2 rising edge enable */
//      uint8_t  FE2                      :  1; /*!< Pin 2 falling edge enable */
//      uint8_t  CLR2                     :  1; /*!< Pin 2 interrupt clear */
//      uint8_t  ACTDET2                  :  1; /*!< Pin 2 activity interrupt */
//      uint8_t                           :  2; /*   (reserved) */
//      uint8_t  DIR3                     :  1; /*!< Pin 3 output enable */
//      uint8_t  IE3                      :  1; /*!< Pin 3 interrupt mask */
//      uint8_t  RE3                      :  1; /*!< Pin 3 rising edge enable */
//      uint8_t  FE3                      :  1; /*!< Pin 3 falling edge enable */
//      uint8_t  CLR3                     :  1; /*!< Pin 3 interrupt clear */
//      uint8_t  ACTDET3                  :  1; /*!< Pin 3 activity interrupt */
//      uint8_t                           :  2; /*   (reserved) */
//    };
    Port_t port[4];
    uint32_t WORD;
  } GPAP03; /* +0x404 */

  union {
    struct {
      uint8_t  DIR4                     :  1; /*!< Pin 4 output enable */
      uint8_t  IE4                      :  1; /*!< Pin 4 interrupt mask */
      uint8_t  RE4                      :  1; /*!< Pin 4 rising edge enable */
      uint8_t  FE4                      :  1; /*!< Pin 4 falling edge enable */
      uint8_t  CLR4                     :  1; /*!< Pin 4 interrupt clear */
      uint8_t  ACTDET4                  :  1; /*!< Pin 4 activity interrupt */
      uint8_t                           :  2; /*   (reserved) */
      uint32_t                          : 24; /*   (reserved) */
    };
    uint32_t WORD;
  } GPAP4; /* +0x408 */

} GPIOA_SFRS_t;

/* --------  End of section using anonymous unions and disabling warnings  -------- */
#if   defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif

/**
 * @brief The starting address of GPIOA SFRS.
 */
#define GPIOA_SFRS ((__IO GPIOA_SFRS_t *)0x50014000)

#endif /* end of __GPIOA_SFR_H__ section */


